1. The Field of the Invention
The present invention relates to semiconductor device manufacturing. More particularly, the present invention is directed to a process for enhancing etch selectivity and uniformity when etching silicon-containing materials in semiconductor device manufacturing.
2. The Relevant Technology
The integrated circuit manufacturing industry is rapidly progressing toward more highly advanced and miniaturized integrated circuits. This progress is effectively revolutionizing the electronics industry due to the higher capability of the electronic devices that can be produced as a result. In order to continue this progress, however, new manufacturing processes are needed which have the capability of producing the finer features that are required. For instance, improved processes are needed to etch substantially normal or anisotropic submicron sidewalls on silicon substrates of in-process integrated semiconductor circuits. New processes are also needed to etch submicron geometric features in films on the silicon substrates to exact depths. Consequently, the new processes must have a high selectivity to photoresist and to pad oxides.
The prior art has utilized methods such as the use of diatomic chloride in ionized plasma etches to emphasize the physical aspects of the etch, so as to produce more anisotropic sidewalls. Etch processes have even been conducted in two stages, a primary etch and a secondary etch, with the secondary etch using less active compounds. However, as features become smaller, even these processes are proving insufficient.
One example of a drawback of current prior art processes is shown in FIG. 1. Therein is shown a line space pair 12 being etched in a film of polysilicon 14. Polysilicon film 14 is formed over a pad oxide 16 on a silicon substrate 10. Above polysilicon film 14 is a patterned layer of photoresist 18. It can be seen from FIG. 1 that the ionized etchant material attacks the exposed surface of polysilicon film 14.
The prior art etch also has a tendency to attack the sidewalls of line space pair 12. This results in undercutting of polysilicon film 14 beneath photoresist layer 18. Furthermore, when using highly reactive etchants such as diatomic chloride, the sidewalls of photoresist layer 18 are also eroded, thereby giving the etchant even greater access to the sidewalls 20 of line space pair 12, and resulting in non-anisotropically sloped sidewalls. This is problematic, as it alters the critical dimensions of the device features. Also, the non-anisotropically sloped sidewalls are undesirable, as it often necessary when forming certain features of integrated circuits, such as gate regions in DRAM memory cells, to etch lines and other graphic features anisotropically. Anisotropic etches are also desirable as they allow for higher device density and consequently, greater integrated circuit miniaturization.
Thus, it can be seen that a need exists in the art for an etch process with which selectivity to both photoresist and oxide can be increased, and which results in a more anisotropic nature of sidewalls in etched geometrical features.